1. Field of the Invention
The present invention relates to a data output apparatus in a memory device, and more particularly to, a data output apparatus improved a data transferring speed by re-amplifying a data amplified by a bitline sense amplifier and transferring it to global input/output lines
2. Description of the Related Art
In general, during a read operation of a memory device, a cell data selected by an address signal is transferred to a local data line after being sensed and amplified by a bitline sense amplifier. Typically, a bitline and a local data line are comprised of a pair, respectively.
However, it is merely about 20 mV for the differences between high level and low level of the data transferred to the local data lines. As a result, it is necessary to perform processes for converting the data to a CMOS voltage level. Those processes are performed by an amplifier(with reference to an amplifier in FIG. 1) disposed between a pair of local data lines. That is, the data of high and low levels transferred to the local data lines are amplified to a driving voltage VDD level and a ground voltage level. Accordingly, the voltage difference between the high and low levels is a VDD. Here, the VDD could be 1.8V, or 2.5V according to kinds of memory devices as a driving voltage applied to the memory device.
Hereinafter, it will be described about a conventional data output apparatus in more detail with reference to FIG.
Referring to FIG. 1, a Main Amplifier Data True MADT is disposed on a local data line receiving data transferred through a bitline BIT, and a Main Amplifier Data Bar MADB is disposed on a local data line receiving data transferred through a bitline /BIT.
An amplifier in FIG. 1 is a circuit for amplifying the data MADT and MADB transferred from the bitlines to a CMOS voltage level. The operation of the amplifier is controlled by a Main Amplifier Enable signal MAE. That is, the amplifier is normally operated while the MAE signal maintains high level.
As described in FIG. 1, transistors P1, N1 and N2 are CMOS type buffer receiving the data MADT and latch INV1, INV2 hold an output signal of the CMOS buffer.
Data MAQ outputted from the latch INV1, INV2 is applied to inverters INV3, INV4, respectively.
An output signal of the inverter INV3 is transferred to a gate of a pull-up transistor P3 through a switch TM1, while an output signal of the inverter INV4 is transferred to a gate of a pull-down transistor N3 through a switch TM2.
The switches TM1, TM2 are controlled by a control signal MAOEB. As shown in FIG. 1, when the control signal MAOEB is low level, the switches TM1, TM2 are turned on to transfer outputs from the inverters INV3, INV4 to the gates of the pull-up transistor P3 and the pull-down transistor N3, respectively. On the other hand, when the control signal MAOEB is high level, the switches TM1, TM2 are turned off. The circuit in FIG. 1 is precharged in case that the control signal MAOEB is high level, while the circuit is normally operated in case that the control signal MAOEB is low level.
When the pull-down transistor N3 is operated, a transistor P2 positioned between a driving voltage VDD and a gate of the pull-up transistor P3 disables the operation of the pull-up transistor P3. As similar to this, when the pull-up transistor P3 is operated, a transistor N4 positioned between a gate of the pull-down transistor N3 and a ground voltage terminal disables the operation of the pull-down transistor N3.
For instance, when the control signal MAOEB is high level which means to be precharged, the transistor P2 disposed between the power source voltage and the pull-up transistor P3, and the transistor N4 disposed between the gate of the pull-down transistor N3 and the ground voltage terminal turn off the transistors P3, P2 according to applying the gate node for the transistor P3 to high level and the gate node for the transistor N3 to low level, respectively. On the other hand, the transistors P2 and N4 maintain to be turned off when the control signal MAOEB is low level.
A global data line gio bus transfers the data generated from the pull-up transistor P2 and the pull-down transistor N4 to a data output driver(not shown in FIG. 1).
Hereinafter, it will be described of an operation of the circuit shown in FIG. 1, with reference to FIG. 2.
Before the control signal MAE which adjusts the operation of the amplifier is enabled to high level, the voltage difference between the data MADT and MADB transferred from the bitlines to the local data lines is very small, as described in FIG. 2. The data MADT is denoted with a dotted line and the data MADB is denoted with a solid line in FIG. 2.
The amplifier is operated when the control signal MAE is transited to high level. Accordingly, the data MADT on the local data line rises to a driving voltage level and the data MADB falls down to a ground voltage level, which means to be developed to the CMOS voltage level.
Further, the output signal MAQB of the CMOS buffer is low level as the data MADT is high level, which results in that the data MAQ outputted from the latch INV1, INV2 is high level.
The inverters INV3, INV4 receive the data MAQ and then invert the data MAQ.
After the whole operations have been done, when the control signal MAOEB is transited to low level, the switches TM1 and TM2 are turned on thereby. Thus, the output signals of the inverters INV3 and INV4 are transferred to the gates for the pull-up transistor P3 and the pull-down transistor N3.
Furthermore, since the data MAQ is high level, the pull-up transistor P3 will be turned on. Accordingly, the data MAQ of high level transfers to the global data line gio bus.
Still referring to FIG. 2, when both data MADT and MADB are high level, the local data lines are precharged. Then, after being precharged, the step that a potential of the data MADT with a dotted line, becomes lower than that of the data MADB illustrates a procedure of transferring data from the bitlines.
A delay time in FIG. 2 is a time from the control signal MAE being enabled to data being outputted to a global data line. Moreover, a Margin is a time from the control signal MAE being enabled to the control signal MAOEB being enabled to low level. Therefore, these delay time and margin are intimately associated with a data transferring speed of a data output apparatus .
However, the conventional apparatus has many delay elements (the inverters INV3, INV4 and the switches TM1 and TM2), so it is difficult to reduce the delay time. Thus, it is not available to use the conventional apparatus for the next generation memory device which operates speedy such as DDR2 SDRAM.